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| a FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 80K Bytes of On-Chip RAM, Configured as 16K Words On-Chip Program Memory RAM and 16K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead TQFP SYSTEM INTERFACE 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory (Mode Selectable) 4 MByte Byte Memory Interface for Storage of Data Tables & Program Overlays 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe & Separate I/O Memory Space Permits "Glueless" System Design (Mode Selectable) Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port *ICE-Port is a trademark of Analog Devices, Inc. DATA ADDRESS GENERATORS DAG 1 DAG 2 PROGRAM SEQUENCER DSP Microcomputer ADSP-2185 FUNCTIONAL BLOCK DIAGRAM POWER-DOWN CONTROL MEMORY 16k 24 PROGRAM MEMORY 16k 16 DATA MEMORY PROGRAMMABLE I/O AND FLAGS FULL MEMORY MODE EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA OR DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT 0 SPORT 1 TIMER INTERNAL DMA PORT HOST MODE ADSP-2100 BASE ARCHITECTURE Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-PortTM* Emulator Interface Supports Debugging in Final Systems GENERAL NOTE This data sheet represents production grade specifications for the ADSP-2185 (5 V). GENERAL DESCRIPTION The ADSP-2185 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2185 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-2185 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2185 is available in 100-pin TQFP package. In addition, the ADSP-2185 supports new instructions, which include bit manipulations--bit set, bit clear, bit toggle, bit test-- new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking, for increased flexibility. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997 ADSP-2185 Fabricated in a high speed, double metal, low power, 0.5 m CMOS process, the ADSP-2185 operates with a 30 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2185's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2185 can: * * * * * generate the next program address fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation The EZ-ICE(R)* performs a full range of functions, including: * * * * * * * * In-target operation Up to 20 breakpoints Single-step or full-speed operation Registers and memory values can be examined and altered PC upload and download functions Instruction-level emulation of program booting and execution Complete assembly and disassembly of instructions C source-level debugging This takes place while the processor continues to: * receive and transmit data through the two serial ports * receive and/or transmit data through the internal DMA port * receive and/or transmit data through the byte DMA port * decrement timer Development System See Designing An EZ-ICE(R)*-Compatible Target System in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as well as the Target Board Connector for EZ-ICE(R)* Probe section of this data sheet for the exact specifications of the EZ-ICE(R)* target board connector. Additional Information The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2185. The System Builder provides a high level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instructionlevel simulation with a reconfigurable user interface to display different portions of the hardware environment. A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundation's GNU C Compiler, generates ADSP-2185 assembly source code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over 100 ANSIstandard mathematical and DSP-specific functions. The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the entire ADSP-21xx family: an ADSP-218x based evaluation board with PC monitor software plus Assembler, Linker, Simulator and PROM Splitter software. The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: * 33 MHz ADSP-2181 * Full 16-bit Stereo Audio I/O with AD1847 SoundPort(R)* Codec * RS-232 Interface to PC with Windows(R) 3.1 Control Software * Stand-Alone Operation with Socketed EPROM * EZ-ICE(R)* Connector for Emulator Control * DSP Demo Programs The ADSP-218x EZ-ICE(R)* Emulator aids in the hardware debugging of an ADSP-2185 system. The emulator consists of hardware, host computer resident software, and the target board connector. The ADSP-2185 integrates on-chip emulation support with a 14-pin ICE-PORTTM* interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICE(R)*s. The ADSP-2185 device need not be removed from the target system when using the EZ-ICE(R)*, nor are any adapters needed. Due to the small footprint of the EZ-ICE(R)* connector, emulation can be supported in final board designs. *All trademarks are the property of their respective holders. *EZ-ICE and SoundPORT are registered trademarks of Analog Devices, Inc. This data sheet provides a general overview of ADSP-2185 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User's Manual. For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet. ARCHITECTURE OVERVIEW The ADSP-2185 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-2185 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. POWER-DOWN CONTROL DATA ADDRESS GENERATORS DAG 1 DAG 2 MEMORY PROGRAM SEQUENCER 16k 24 PROGRAM MEMORY 16k 16 DATA MEMORY PROGRAMMABLE I/O AND FLAGS FULL MEMORY MODE EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA OR DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT 0 SPORT 1 TIMER INTERNAL DMA PORT HOST MODE ADSP-2100 BASE ARCHITECTURE Figure 1. Block Diagram Figure 1 is an overall block diagram of the ADSP-2185. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. -2- REV. 0 ADSP-2185 The internal result (R) bus connects the computational units so the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2185 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from data memory and program memory. Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use of five internal buses: * Program Memory Address (PMA) Bus * Program Memory Data (PMD) Bus * Data Memory Address (DMA) Bus * Data Memory Data (DMD) Bus * Result (R) Bus The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the ADSP-2185 to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP2185 can fetch an operand from program memory and the next instruction in the same cycle. When configured in host mode, the ADSP-2185 has a 16-bit Internal DMA port (IDMA port) for connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM. An interface to low cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH and BG). One execution mode (Go Mode) allows the ADSP-2185 to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. The ADSP-2185 can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two level-sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a REV. 0 wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The ADSP-2185 provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports The ADSP-2185 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2185 SPORTs. For additional information on Serial Ports, refer to the ADSP2100 Family User's Manual. * SPORTs are bidirectional and have a separate, double-buffered transmit and receive section. * SPORTs can use an external serial clock or generate their own serial clock internally. * SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulse widths and timings. * SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and -law companding according to CCITT recommendation G.711. * SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. * SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. * SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream. * SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration. PIN DESCRIPTIONS The ADSP-2185 will be available in a 100-lead TQFP package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. -3- ADSP-2185 Common-Mode Pins Pin Name(s) # of Pins Input/ Output Function Memory Interface Pins RESET BR BG BGH DMS PMS IOMS BMS CMS RD WR IRQ2/ PF7 IRQL0/ PF5 IRQL1/ PF6 IRQE/ PF4 PF3 Mode C/ PF2 Mode B/ PF1 Mode A/ PF0 CLKIN, XTAL CLKOUT SPORT0 SPORT1/ IRQ1:0 FI, FO PWD PWDACK FL0, FL1, FL2 VDD and GND EZ-Port 1 1 1 1 1 1 1 1 1 1 1 1 I I O O O O O O O O O I I/O I I/O I I/O I I/O I/O I I/O 1 1 1 1 1 1 I I/O 1 I I/O 2 1 5 5 I O I/O I/O 1 1 3 16 9 I O O I I/O Processor Reset Input Bus Request Input Bus Grant Output Bus Grant Hung Output Data Memory Select Output Program Memory Select Output Memory Select Output Byte Memory Select Output Combined Memory Select Output Memory Read Enable Output Memory Write Enable Output Edge- or Level-Sensitive Interrupt Request1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Edge-Sensitive Interrupt Requests1 Programmable I/O Pin Programmable I/O Pin Mode Select Input--Checked only During RESET Programmable I/O Pin During Normal Operation Mode Select Input--Checked only During RESET Programmable I/O Pin During Normal Operation Mode Select Input--Checked only During RESET Programmable I/O Pin During Normal Operation Clock or Quartz Crystal Input Processor Clock Output Serial Port I/O Pins Serial Port I/O Pins Edge- or Level-Sensitive Interrupts, Flag In, Flag Out2 Power-Down Control Input Power-Down Control Output Output Flags Power and Ground For Emulation Use The ADSP-2185 processor can be used in one of two modes, Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. Full Memory Mode Pins (Mode C = 0) Pin Name A13:0 # of Pins 14 Input/ Output O Function Address Output Pins for Program, Data, Byte and I/O Spaces Data I/O Pins for Program, Data, Byte and I/O Spaces (8 MSBs Are Also Used as Byte Memory Addresses) D23:0 24 I/O Host Mode Pins (Mode C = 1) Pin Name IAD15:0 A0 D23:8 IWR IRD IAL IS IACK # of Pins 16 1 16 1 1 1 1 1 Input/ Output I/O O I/O I I I I O Function IDMA Port Address/Data Bus Address Pin for External I/O, Program, Data, or Byte Access Data I/O Pins for Program, Data Byte and I/O Spaces IDMA Write Enable IDMA Read Enable IDMA Address Latch Pin IDMA Select IDMA Port Acknowledge In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals Setting Memory Mode Memory Mode selection for the ADSP-2185 is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP's PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive. Passive configuration involves the use a pull-up or pull-down resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down, on the order of 100 k, can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor's output driver. For minimum power consumption during power-down, reconfigure PF2 to be an input as the pull-up or pull-down will hold the pin in a known state and will not switch. Active configuration involves the use of a three-stateable external driver connected to the Mode C pin. A driver's output enable should be connected to the DSP's RESET signal such that it only drives the PF2 pin when RESET is active (low). After -4- REV. 0 NOTES 1 Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. 2 SPORT configuration determined by the DSP System Control Register. Software configurable. ADSP-2185 RESET is deasserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant level and not oscillate should the three-state driver's level hover around the logic switching point. Interrupts The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are twelve levels deep to allow interrupt, loop and subroutine nesting. The following instructions allow global enable or disable servicing of the interrupts (including power-down), regardless of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA. ENA INTS; DIS INTS; When the processor is reset, interrupt servicing is enabled. LOW POWER OPERATION The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. The ADSP-2185 provides four dedicated external interrupt input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the PF7:4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six external interrupts. The ADSP-2185 also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset). The IRQ2, IRQ0 and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table I. Table I. Interrupt Priority & Interrupt Vector Addresses The ADSP-2185 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: * Power-Down * Idle * Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation. Power-Down Source Of Interrupt Reset (or Power-Up with PUCR = 1) Power-down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer Interrupt Vector Address (Hex) 0000 (Highest Priority) 002C 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 (Lowest Priority) The ADSP-2185 processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control. Here is a brief list of power-down features. Refer to the ADSP-2100 Family User's Manual, "System Interface" chapter, for detailed information about the powerdown feature. * Quick recovery from power-down. The processor begins executing instructions in as few as 100 CLKIN cycles. * Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power-down without affecting the lowest power rating and 100 CLKIN cycle recovery. * Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 100 CLKIN cycle start-up. * Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. * Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The powerdown interrupt also can be used as a nonmaskable, edgesensitive interrupt. * Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. * The RESET pin also can be used to terminate power-down. * Power-down acknowledge pin indicates when the processor has entered power-down. Interrupt routines can either be nested, with higher priority interrupts taking precedence, or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. The ADSP-2185 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1 and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level-sensitive interrupts. REV. 0 -5- ADSP-2185 Idle HOST MEMORY MODE When the ADSP-2185 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals still occur. Slow Idle ADSP-2185 1/2x CLOCK OR CRYSTAL CLKIN ADDR13-0 XTAL FL0-2 PF3 IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6 MODE C/PF2 MODE B/PF1 MODE A/PF0 IOMS A13-0 24 DATA23-0 BMS A10-0 ADDR D23-8 DATA CS ADDR D23-0 DATA PMS DMS CMS BR BG BGH PWD PWDACK D23-16 D15-8 DATA CS A0-A21 14 A13-0 BYTE MEMORY The IDLE instruction is enhanced on the ADSP-2185 to let the processor's internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is IDLE (n); where n = 16, 32, 64 or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor's other internal clock signals, such as SCLK, CLKOUT and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the processor's internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2185 will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64 or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor's reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). SYSTEM INTERFACE I/O SPACE (PERIPHERALS) 2048 LOCATIONS SPORT1 SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI OVERLAY MEMORY TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS SPORT0 SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0 HOST MEMORY MODE ADSP-2185 1/2x CLOCK OR CRYSTAL CLKIN A0 XTAL FL0-2 PF3 DATA23-0 IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6 MODE C/PF2 MODE B/PF1 MODE A/PF0 BMS 16 1 SPORT1 SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI IOMS SPORT0 SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0 PMS DMS CMS BR BG BGH PWD PWDACK IDMA PORT SYSTEM INTERFACE OR CONTROLLER IRD/D6 IWR/D7 IS/D4 IAL/D5 IACK/D3 IAD15-0 Figure 2 shows typical basic system configurations with the ADSP-2185, two serial devices, a byte-wide EPROM and optional external program and data overlay memories (mode selectable). Programmable wait state generation allows the processor to easily connect to slow peripheral devices. The ADSP-2185 also provides four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals. 16 Figure 2. Basic System Configuration Clock Signals The ADSP-2185 can be clocked by either a crystal or a TTLcompatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9, ADSP-2100 Family User's Manual, for detailed information on this power-down feature. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor's CLKIN input. When an external clock is used, the XTAL input must be left unconnected. -6- REV. 0 ADSP-2185 The ADSP-2185 uses an input clock with a frequency equal to half the instruction rate; a 16.67 MHz input clock yields a 30 ns processor cycle (which is equivalent to 33 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because the ADSP-2185 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. MEMORY ARCHITECTURE The ADSP-2185 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory and I/O. Program Memory is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-2185 has 16K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces using the external data bus. Both an instruction opcode and a data value can be read from on-chip program memory in a single cycle. Data Memory is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2185 has 16K words on Data Memory RAM on chip, consisting of 16,352 user-accessible locations and 32 memorymapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. Byte Memory (Full Memory Mode) provides access to an 8-bit wide memory space through the Byte DMA (BDMA) port. The Byte Memory interface provides access to 4 MBytes of memory by utilizing eight data lines as additional address lines. This gives the BDMA Port an effective 22-bit address range. On power-up, the DSP can automatically load bootstrap code from byte memory. I/O Space (Full Memory Mode) allows access to 2048 locations of 16-bit-wide data. It is intended to be used to communicate with parallel peripheral devices such as data converters and external registers or latches. Program Memory CLKIN XTAL CLKOUT DSP Figure 3. External Crystal Connections Reset The RESET signal initiates a master reset of the ADSP-2185. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulse width specification, tRSP. The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. The ADSP-2185 contains a 16K x 24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. In addition, the ADSP-2185 allows the use of 8K external memory overlays. The program memory space organization is controlled by the Mode B pin and the PMOVLAY register. Normally, the ADSP2185 is configured with Mode B = 0 and program memory organized as shown in Figure 4. PROGRAM MEMORY ADDRESS 0x3FFF 8K INTERNAL (PMOVLAY = 0, MODE B = 0) OR EXTERNAL 8K (PMOVLAY = 1 or 2, MODE B = 0) 0x2000 0x1FFF 8K INTERNAL 0x0000 Figure 4. Program Memory (Mode B = 0) There are 16K words of memory accessible internally when the PMOVLAY register is set to 0. When PMOVLAY is set to something other than 0, external accesses occur at addresses 0x2000 through 0x3FFF. The external address is generated as shown in Table II. REV. 0 -7- ADSP-2185 Table II. PMOVLAY Memory 0 1 Internal External Overlay 1 External Overlay 2 A13 A12:0 2 Not Applicable Not Applicable 0 13 LSBs of Address Between 0x2000 and 0x3FFF 1 13 LSBs of Address Between 0x2000 and 0x3FFF There are 16,352 words of memory accessible internally when the DMOVLAY register is set to 0. When DMOVLAY is set to something other than 0, external accesses occur at addresses 0x0000 through 0x1FFF. The external address is generated as shown in Table III. Table III. DMOVLAY Memory 0 1 Internal External Overlay 1 External Overlay 2 A13 A12:0 This organization provides for two external 8K overlay segments using only the normal 14 address bits. This allows for simple program overlays using one of the two external segments in place of the on-chip memory. Care must be taken in using this overlay space in that the processor core (i.e., the sequencer) does not take into account the PMOVLAY register value. For example, if a loop operation was occurring on one of the external overlays and the program changes to another external overlay or internal memory, an incorrect loop operation could occur. In addition, care must be taken in interrupt service routines as the overlay registers are not automatically saved and restored on the processor mode stack. When Mode B = 1, booting is disabled and overlay memory is disabled (PMOVLAY must be 0). Figure 5 shows the memory map in this configuration. PROGRAM MEMORY ADDRESS 0x3FFF 2 Not Applicable Not Applicable 13 LSBs of Address 0 Between 0x2000 and 0x3FFF 13 LSBs of Address 1 Between 0x2000 and 0x3FFF This organization allows for two external 8K overlays using only the normal 14 address bits. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register. I/O Space (Full Memory Mode) INTERNAL 8K (PMOVLAY = 0, MODE B = 1) 0x2000 0x1FFF The ADSP-2185 supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals or to bus interface ASIC data registers. I/O space supports 2048 locations. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated 3-bit wait state registers, IOWAIT0-3, which specify up to seven wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table IV. Table IV. 8K EXTERNAL 0x0000 Address Range Figure 5. Program Memory (Mode B = 1) Data Memory Wait State Register IOWAIT0 IOWAIT1 IOWAIT2 IOWAIT3 The ADSP-2185 has 16,352 16-bit words of internal data memory. In addition, the ADSP-2185 allows the use of 8K external memory overlays. Figure 6 shows the organization of the data memory. DATA MEMORY 32 MEMORY- MAPPED REGISTERS ADDRESS 0x3FFF 0x3FEO 0x3FDF INTERNAL 8160 WORDS 0x2000 8K INTERNAL (DMOVLAY = 0) OR EXTERNAL 8K (DMOVLAY = 1, 2) 0x1FFF 0x000-0x1FF 0x200-0x3FF 0x400-0x5FF 0x600-0x7FF Composite Memory Select (CMS) The ADSP-2185 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS), but can combine their functionality. When set, each bit in the CMSSEL register causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory and use either DMS or PMS as the additional address bit. The CMS pin functions as the other memory select signals, with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the -8- REV. 0 0x0000 Figure 6. Data Memory ADSP-2185 selected memory select signal. All enable bits, except the BMS bit, default to 1 at reset, Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K x 8. The byte memory space on the ADSP-2185 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg x 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register. Byte Memory DMA (BDMA, Full Memory Mode) create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor and to start execution at address 0 when the BDMA accesses have completed. Internal Memory DMA Port (IDMA Port; Host Memory Mode) The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8-, 16- or 24-bit word transferred. The BDMA circuit supports four different data formats, which are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table V shows the data formats supported by the BDMA circuit. Table V. The IDMA Port provides an efficient means of communication between a host system and the ADSP-2185. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP's memorymapped control registers. The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to while the ADSP2185 is operating at full speed. The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the IDMAA register. Once the address is stored, data can then be either read from or written to the ADSP-2185's on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-2185 that a particular transaction is required. In either case, there is a one-processorcycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Bootstrap Loading (Booting) BTYPE 00 01 10 11 Internal Memory Space Program Memory Data Memory Data Memory Data Memory Word Size 24 16 8 8 Alignment Full Word Full Word MSBs LSBs Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory, regardless of the values of Mode B, PMOVLAY or DMOVLAY. When the BWCOUNT register is written with a nonzero value, the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to REV. 0 The ADSP-2185 has two mechanisms to allow automatic loading of the internal program memory after reset. The method for booting is controlled by the Mode A, B and C configuration bits as shown in Table VI. These four states can be compressed into two-state bits by allowing an IDMA boot with Mode C = 1. However, three bits are used to ensure future compatibility with parts containing internal program memory ROM. BDMA Booting When the MODE pins specify BDMA booting, the ADSP-2185 initiates a BDMA boot sequence when RESET is released. -9- ADSP-2185 Table VI. Boot Summary Table IDMA Port Booting MODE C MODE B MODE A Booting Method 0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode. No Automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used but the processor does not automatically use or wait for these operations. BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. Additional interface hardware is required. IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. The ADSP-2185 can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the ADSP-2185 boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program execution is held off until on-chip program memory location 0 is written to. The ADSP-2100 Family development software (Revision 5.02 and later) can generate IDMA compatible boot code. Bus Request & Bus Grant 0 1 0 The ADSP-2185 can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP-2185 is not performing an external memory access, it responds to the active BR input in the following processor cycle by: * Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, * Asserting the bus grant (BG) signal and * Halting program execution. If Go Mode is enabled, the ADSP-2185 will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2185 is performing an external memory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, reenables the output drivers and continues program execution from the point where it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-2185 is ready to execute an instruction but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-2185 deasserts BG and BGH and executes the external memory access. Flag I/O Pins 1 0 0 1 0 1 The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD and BEAD registers are set to 0; the BTYPE register is set to 0 to specify program memory 24 bit words; and the BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the ADSP-2185. The only memory address bit provided by the processor is A0. The ADSP-2185 has eight general purpose programmable input/ output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-2185's clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, the ADSP-2185 has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORT1. Note: Pins PF0, PF1 and PF2 are also used for device configuration during reset. -10- REV. 0 ADSP-2185 BIASED ROUNDING I/O Space Instructions A mode is available on the ADSP-2185 to allow biased rounding in addition to the normal unbiased rounding. When the BIASRND bit is set to 0, the normal unbiased rounding operations occur. When the BIASRND bit is set to 1, biased rounding occurs instead of the normal unbiased rounding. When operating in biased rounding mode all rounding operations with MR0 set to 0x8000 will round up, rather than only rounding up odd MR1 values. For example: Table VII. The instructions used to access the ADSP-2185's I/O memory space are as follows: Syntax: IO(addr) = dreg dreg = IO(addr); where addr is an address value between 0 and 2047 and dreg is any of the 16 data registers. Examples: IO(23) = AR0; AR1 = IO(17); Description: The I/O space read and write instructions move data between the data registers and the I/O memory space. DESIGNING AN EZ-ICE (R)*-COMPATIBLE SYSTEM MR Value Before RND 00-0000-8000 00-0001-8000 00-0000-8001 00-0001-8001 00-0000-7FFF 00-0001-7FFF Biased RND Result 00-0001-8000 00-0002-8000 00-0001-8001 00-0002-8001 00-0000-7FFF 00-0001-7FFF Unbiased RND Result 00-0000-8000 00-0002-8000 00-0001-8001 00-0002-8001 00-0000-7FFF 00-0001-7FFF This mode only has an effect when the MR0 register contains 0x8000; all other rounding operations work normally. This mode allows more efficient implementation of bit-specified algorithms that use biased rounding, for example the GSM speech compression routines. Unbiased rounding is preferred for most algorithms. Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer Control register. Instruction Set Description The ADSP-2185 has on-chip emulation support and an ICE-PortTM*, a special set of pins that interface to the EZ-ICE(R)*. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE(R)*. Target systems must have a 14-pin connector to accept the EZ-ICE(R)*'s in-circuit probe, a 14-pin plug. See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products. The ICE-PortTM* interface consists of the following ADSP-2185 pins: EBR EBG ERESET EMS EINT ECLK ELIN ELOUT EE These ADSP-2185 pins must be connected only to the EZ-ICE(R)* connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-2185 and the connector must be kept as short as possible, no longer than three inches. The following pins are also used by the EZ-ICE(R)*: BR BG RESET GND The EZ-ICE(R)* uses the EE (emulator enable) signal to take control of the ADSP-2185 in the target system. This causes the processor to use its ERESET, EBR and EBG pins instead of the RESET, BR and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. The EZ-ICE(R)* connects to your target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. The ADSP-2185 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor's unique architecture, offers the following benefits: * The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. * Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. * The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to use on-chip memory and conform to the ADSP2185's interrupt vector and reset vector map. * Sixteen condition codes are available. For conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. * Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. REV. 0 -11- ADSP-2185 Target Board Connector for EZ-ICE (R)* Probe The EZ-ICE(R)* connector (a standard pin strip header) is shown in Figure 7. You must add this connector to your target board design if you intend to use the EZ-ICE(R)*. Be sure to allow enough room in your system to fit the EZ-ICE(R)* probe onto the 14-pin connector. 1 GND 3 EBG Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing requirements within published limits. Restriction: All memory strobe signals on the ADSP-2185 (RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your target system must have 10 k pull-up resistors connected when the EZ-ICE(R)* is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE(R)* debugging sessions. These resistors may be removed at your option when the EZ-ICE(R)* is not being used. Target System Interface Signals 2 4 BG BR 5 EBR 6 EINT KEY (NO PIN) ELOUT x 9 7 8 ELIN 10 ECLK 11 EE 12 EMS RESET 13 14 ERESET When the EZ-ICE(R)* board is installed, the performance on some system signals change. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE(R)* board: * EZ-ICE(R)* emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal. * EZ-ICE(R)* emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal. * EZ-ICE(R)* emulation ignores RESET and BR when singlestepping. * EZ-ICE(R)* emulation ignores RESET and BR when in Emulator Space (DSP halted). * EZ-ICE(R)* emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP's external memory bus only if bus grant (BG) is asserted by the EZ-ICE(R)* board's DSP. TOP VIEW Figure 7. Target Board Connector for EZ-ICE(R)* The 14-pin, 2-row pin strip header is keyed at the Pin 7 location--you must remove Pin 7 from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 x 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE(R)* probe plug. Pin strip headers are available from vendors such as 3M, McKenzie and Samtec. Target Memory Interface For your target system to be compatible with the EZ-ICE(R)* emulator, it must comply with the memory interface guidelines listed below. PM, DM, BM, IOM and CM Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM) and Composite Memory (CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in this DSP's data sheet. The performance of the EZ-ICE(R)* may approach published worst case specification for some memory access timing requirements and switching characteristics. -12- REV. 0 ADSP-2185 RECOMMENDED OPERATING CONDITIONS K Grade Parameter VDD TAMB Min 4.5 0 Max 5.5 +70 Min 4.5 -40 B Grade Max 5.5 +85 Unit V C ELECTRICAL CHARACTERISTICS Parameter VIH VIH VIL VOH Hi-Level Input Voltage1, 2 Hi-Level CLKIN Voltage Lo-Level Input Voltage1, 3 Hi-Level Output Voltage1, 4, 5 Test Conditions @ VDD = max @ VDD = max @ VDD = min @ VDD = min IOH = -0.5 mA @ VDD = min IOH = -100 A6 @ VDD = min IOL = 2 mA @ VDD = max VIN = VDDmax @ VDD = max VIN = 0 V @ VDD = max VIN = VDDmax8 @ VDD = max VIN = 0 V8 @ VDD = 5.0 @ VDD = 5.0 TAMB = +25C tCK = 30 ns11 @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25C Min 2.0 2.2 0.8 2.4 VDD - 0.3 0.4 10 10 10 10 12.4 K/B Grades Typ Max Unit V V V V V V A A A A mA VOL IIH IIL IOZH IOZL IDD IDD CI CO Lo-Level Output Voltage1, 4, 5 Hi-Level Input Current3 Lo-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current7 Supply Current (Idle)9 Supply Current (Dynamic)10 Input Pin Capacitance3, 6, 12 Output Pin Capacitance6, 7, 12, 13 63 8 mA pF 8 pF NOTES 1 Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7. 2 Input only pins: RESET, BR, DR0, DR1, PWD. 3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH. 5 Although specified for TTL outputs, all ADSP-2185 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0-PF7. 8 0 V on BR, CLKIN Inactive. 9 Idle refers to ADSP-2185 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. 10 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11 VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. 12 Applies to TQFP package type. 13 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice. REV. 0 -13- ADSP-2185 ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . +280C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD SENSITIVITY The ADSP-2185 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur to devices subjected to high energy electrostatic discharges. The ADSP-2185 features proprietary ESD protection circuitry to dissipate high energy discharges (Human Body Model) per method 3015 of MIL-STD-883. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination before devices are removed. WARNING! ESD SENSITIVE DEVICE ADSP-2185 TIMING PARAMETERS GENERAL NOTES MEMORY TIMING SPECIFICATIONS Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times. TIMING NOTES The table below shows common memory device specifications and the corresponding ADSP-2185 timing parameters, for your convenience. Memory Device Specification Address Setup to Write Start Address Setup to Write End Address Hold Time Data Setup Time ADSP-2185 Timing Timing Parameter Parameter Definition tASW tAW tWRA tDW A0-A13, xMS Setup before WR Low A0-A13, xMS Setup before WR Deasserted A0-A13, xMS Hold before WR Low Data Setup before WR High Data Hold after WR High RD Low to Data Valid A0-A13, xMS to Data Valid Switching characteristics specify how the processor changes its signals. You have no control over this timing--circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Data Hold Time tDH OE to Data Valid tRDD Address Access Time tAA xMS = PMS, DMS, BMS, CMS, IOMS. FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS tCK is defined as 0.5tCKI. The ADSP-2185 uses an input clock with a frequency equal to half the instruction rate: a 16.67 MHz input clock (which is equivalent to 60 ns) yields a 30 ns processor cycle (equivalent to 33 MHz). tCK values within the range of 0.5tCKI period should be substituted for all relevant timing parameters to obtain the specification value. Example: tCKH = 0.5tCK - 7 ns = 0.5 (30 ns) - 7 ns = 8 ns -14- REV. 0 ADSP-2185 ENVIRONMENTAL CONDITIONS 2185 POWER, INTERNAL1, 3, 4 440 420 400 380 POWER (PINT) - mW 360 340 320 300 280 260 240 VDD = 4.5V 214mW 29 30 31 32 1/tCK - MHz 33 34 220 200 28 277mW 243mW VDD = 5.0V 315mW 349mW VDD = 5.5V 396mW Ambient Temperature Rating: TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W CA = Thermal Resistance (Case-to-Ambient) JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) Package TQFP JA JC CA 50C/W 2C/W 48C/W POWER DISSIPATION POWER, IDLE1, 2 95 90 85 POWER (PIDLE) - mW 80 75 75mW 70 65 60 55 50 45 40 28 40mW 29 VDD = 4.5V 30 31 32 1/fCK - MHz 45mW 56mW VDD = 5.0V 62mW 83mW VDD = 5.5V To determine total power dissipation in a specific application, the following equation should be applied for each output: C x VDD2 x f C = load capacitance, f = output switching frequency. Example: In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions: * External data memory is accessed every cycle with 50% of the address pins switching. * External data memory writes occur every other cycle with 50% of the data pins switching. * Each address and data pin has a 10 pF total load at the pin. * The application operates at VDD = 5.0 V and tCK = 30 ns. Total Power Dissipation = PINT + (C x VDD2 x f) PINT = internal power dissipation from Power vs. Frequency graph (Figure 8). (C x VDD x f) is calculated for each output: 2 33 34 POWER, IDLE n MODES3 75 70 65 POWER (PIDLEn) - mW 60 56mW 55 50 45 40 35 30 34mW 38mW 36mW 36mW IDLE (16) IDLE (128) 62mW IDLE # of Pins Address, DMS Data Output, WR RD CLKOUT 8 9 1 1 C x 10 pF x 10 pF x 10 pF x 10 pF VDD2 x5 V x 52 V x 52 V x 52 V 2 f x 33.3 MHz = 66.6 mW x 16.67 MHz = 37.5 mW x 16.67 MHz = 4.2 mW x 33.3 MHz = 8.3 mW 25 28 29 30 31 32 1/fCK - MHz 33 34 VALID FOR ALL TEMPERATURE GRADES. 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2IDLE REFERS TO ADSP-2185 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND. 3TYPICAL 4I DD 116.6 mW Total power dissipation for this example is PINT + 116.6 mW. POWER DISSIPATION AT 5.0V VDD AND 25C EXCEPT WHERE SPECIFIED. MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. Figure 8. Power vs. Frequency REV. 0 -15- ADSP-2185 CAPACITIVE LOADING Figures 9 and 10 show the capacitive loading characteristics of the ADSP-2185. 30 T = +85C VDD = 4.5V 25 is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. INPUT 1.5V RISE TIME (0.4V-2.4V) - ns 20 OUTPUT 2.0V 1.5V 0.3V 15 10 Figure 11. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Enable Time 5 0 0 50 100 150 CL - pF 200 250 300 Figure 9. Typical Output Rise Time vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) 18 16 VALID OUTPUT DELAY OR HOLD - ns 14 12 10 8 6 4 2 NOMINAL -2 -4 -6 0 50 100 CL - pF 150 200 250 Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. REFERENCE SIGNAL tMEASURED tENA VOH (MEASURED) VOH (MEASURED) - 0.5V OUTPUT VOL (MEASURED) +0.5V VOL (MEASURED) 1.0V VOL (MEASURED) OUTPUT STARTS DRIVING 2.0V tDIS VOH (MEASURED) tDECAY OUTPUT STOPS DRIVING HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V. Figure 12. Output Enable/Disable IOL Figure 10. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: tDECAY = CL x 0.5V iL TO OUTPUT PIN 50pF +1.5V IOH Figure 13. Equivalent Device Loading for AC Measurements (Including All Fixtures) from which tDIS = tMEASURED - tDECAY -16- REV. 0 ADSP-2185 TIMING PARAMETERS Parameter Clock Signals and Reset Timing Requirements: tCKI CLKIN Period tCKIL CLKIN Width Low tCKIH CLKIN Width High Switching Characteristics: tCKL CLKOUT Width Low tCKH CLKOUT Width High tCKOH CLKIN High to CLKOUT High Control Signals Timing Requirements: RESET Width Low1 tRSP tMS Mode Setup Before RESET High tMH Mode Setup After RESET High 5 tCK 2 5 ns ns ns 60 20 20 0.5 tCK - 7 0.5 tCK - 7 0 150 ns ns ns ns ns ns Min Max Unit 20 NOTE 1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). tCKI tCKIH CLKIN tCKIL tCKCH tCKH CLKOUT tCKL PF(2:0)* tMS RESET tMH *PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 14. Clock Signals REV. 0 -17- ADSP-2185 Parameter Interrupts and Flag Timing Requirements: tIFS IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 tIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 Switching Characteristics: tFOH Flag Output Hold after CLKOUT Low5 tFOD Flag Output Delay from CLKOUT Low5 Min Max Unit 0.25 tCK + 15 0.25 tCK 0.5 tCK - 7 0.25 tCK + 5 ns ns ns ns NOTES 1 If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to "Interrupt Controller Operation" in the Program Control chapter of the ADSP-2100 Family User's Manual for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE. 4 PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5 Flag outputs = PFx, FL0, FL1, FL2, Flag_out 4. tFOD CLKOUT tFOH FLAG OUTPUTS tIFH IRQx FI PFx tIFS Figure 15. Interrupts and Flags -18- REV. 0 ADSP-2185 Parameter Bus Request/Grant Timing Requirements: tBH BR Hold after CLKOUT High1 tBS BR Setup before CLKOUT Low1 Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable tSDB xMS, RD, WR Disable to BG Low tSE BG High to xMS, RD, WR Enable tSEC xMS, RD, WR Enable to CLKOUT Hig tSDBH xMS, RD, WR Disable to BGH Low2 tSEH BGH High to xMS, RD, WR Enable2 0.25 tCK + 2 0.25 tCK + 17 0.25 tCK + 10 0 0 0.25 tCK - 7 0 0 ns ns ns ns ns ns ns ns Min Max Unit NOTES xMS = PMS, DMS, CMS, IOMS, BMS 1 BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User's Manual for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. tBH CLKOUT BR tBS CLKOUT PMS, DMS BMS, RD WR tSD tSEC BG tSDB tSE BGH tSDBH tSEH Figure 16. Bus Request-Bus Grant REV. 0 -19- ADSP-2185 Parameter Memory Read Timing Requirements: tRDD RD Low to Data Valid tAA A0-A13, xMS to Data Valid tRDH Data Hold from RD High Switching Characteristics: RD Pulse Width tRP tCRD CLKOUT High to RD Low tASR A0-A13, xMS Setup before RD Low tRDA A0-A13, xMS Hold after RD Deasserted tRWR RD High to RD or WR Low w = wait states x tCK xMS = PMS, DMS, CMS, IOMS, BMS Min Max Unit 0.5 tCK - 9 + w 0.75 tCK - 10.5 + w 0 0.5 tCK - 5 + w 0.25 tCK - 5 0.25 tCK - 6 0.25 tCK - 3 0.5 tCK - 5 ns ns ns ns ns ns ns ns 0.25 tCK + 7 CLKOUT A0-A13 DMS, PMS, BMS, IOMS, CMS tRDA RD tASR tCRD D tRP tRWR tAA WR tRDD tRDH Figure 17. Memory Read -20- REV. 0 ADSP-2185 Parameter Memory Write Switching Characteristics: tDW Data Setup before WR High tDH Data Hold after WR High tWP WR Pulse Width tWDE WR Low to Data Enabled tASW A0-A13, xMS Setup before WR Low tDDR Data Disable before WR or RD Low tCWR CLKOUT High to WR Low tAW A0-A13, xMS, Setup before WR Deasserted tWRA A0-A13, xMS Hold after WR Deasserted tWWR WR High to RD or WR Low w = wait states x tCK xMS = PMS, DMS, CMS, IOMS, BMS Min Max Unit 0.5 tCK - 7+ w 0.25 tCK - 2 0.5 tCK - 5 + w 0 0.25 tCK - 6 0.25 tCK - 7 0.25 tCK - 5 0.75 tCK - 9 + w 0.25 tCK - 3 0.5 tCK - 5 0.25 tCK + 7 ns ns ns ns ns ns ns ns ns ns CLKOUT A0-A13 DMS, PMS, BMS, CMS, IOMS tWRA WR tASW tAW tCWR D tWP tDH tWWR tDDR tDW tWDE RD Figure 18. Memory Write REV. 0 -21- ADSP-2185 Parameter Serial Ports Timing Requirements: tSCK SCLK Period tSCS DR/TFS/RFS Setup before SCLK Low tSCH DR/TFS/RFS Hold after SCLK Low tSCP SCLKIN Width Switching Characteristics: tCC CLKOUT High to SCLKOUT tSCDE SCLK High to DT Enable tSCDV SCLK High to DT Valid tRH TFS/RFSOUT Hold after SCLK High tRD TFS/RFSOUT Delay from SCLK High tSCDH DT Hold after SCLK High tTDE TFS (Alt) to DT Enable tTDV TFS (Alt) to DT Valid tSCDD SCLK High to DT Disable tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 50 4 7 20 0.25 tCK 0 0 15 0 0 14 15 15 0.25 tCK + 10 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max Unit CLKOUT tCC tCC tSCK tSCP SCLK tSCS DR TFSIN RFSIN tSCH tSCP tRD tRH RFSOUT TFSOUT tSCDV tSCDE DT tSCDD tSCDH tTDE tTDV TFSOUT ALTERNATE FRAME MODE tRDV RFSOUT MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) tTDE tTDV TFSIN ALTERNATE FRAME MODE tRDV RFSIN MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) Figure 19. Serial Ports -22- REV. 0 ADSP-2185 Parameter IDMA Address Latch Timing Requirements: tIALP Duration of Address Latch1, 3 tIASU IAD15-0 Address Setup before Address Latch End3 tIAH IAD15-0 Address Hold after Address Latch End3 tIKA IACK Low before Start of Address Latch1 tIALS Start of Write or Read after Address Latch End2, 3 NOTES 1 Start of Address Latch = IS Low and IAL High. 2 Start of Write or Read = IS Low and IWR Low or IRD Low. 3 End of Address Latch = IS High or IAL Low. Min Max Unit 10 5 2 0 3 ns ns ns ns ns IACK tIKA IAL tIALP IS tIASU IAD 15-0 tIAH IRD OR IWR tIALS Figure 20. IDMA Address Latch REV. 0 -23- ADSP-2185 Parameter IDMA Write, Short Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 tIWP Duration of Write1, 2 tIDSU IAD15-0 Data Setup before End of Write2, 3, 4 tIDH IAD15-0 Data Hold after End of Write2, 3, 4 Switching Characteristics: tIKHW Start of Write to IACK High NOTES 1 Start of Write = IS Low and IWR Low. 2 End of Write = IS High or IWR High. 3 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 4 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. Min Max Unit 0 15 5 2 15 ns ns ns ns ns tIKW IACK tIKHW IS tIWP IWR tIDSU IAD 15-0 DATA tIDH Figure 21. IDMA Write, Short Write Cycle -24- REV. 0 ADSP-2185 Parameter IDMA Write, Long Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 tIKSU IAD15-0 Data Setup before IACK Low2, 3, 4 tIKH IAD15-0 Data Hold after IACK Low2, 3, 4 Switching Characteristics: Start of Write to IACK Low4 tIKLW tIKHW Start of Write to IACK High 0 0.5 tCK + 10 2 1.5 tCK 15 ns ns ns ns ns Min Max Unit NOTES 1 Start of Write = IS Low and IWR Low. 2 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 3 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User's Manual. tIKW IACK tIKHW tIKLW IS IWR tIKSU IAD 15-0 DATA tIKH Figure 22. IDMA Write, Long Write Cycle REV. 0 -25- ADSP-2185 Parameter IDMA Read, Long Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 tIRP Duration of Read1 Switching Characteristics: IACK High after Start of Read1 tIKHR tIKDS IAD15-0 Data Setup before IACK Low tIKDH IAD15-0 Data Hold after End of Read2 tIKDD IAD15-0 Data Disabled after End of Read2 tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read tIRDH1 IAD15-0 Previous Data Hold after Start of Read (DM/PM1)3 tIRDH2 IAD15-0 Previous Data Hold after Start of Read (PM2)4 NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. 3 DM read or first half of PM read. 4 Second half of PM read. Min Max Unit 0 15 15 0.5 tCK - 10 0 10 0 15 2 tCK - 5 tCK - 5 ns ns ns ns ns ns ns ns ns ns IACK tIKR IS tIKHR tIRP IRD tIRDE IAD 15-0 PREVIOUS DATA tIKDS READ DATA tIKDH tIRDV tIRDH tIKDD Figure 23. IDMA Read, Long Read Cycle -26- REV. 0 ADSP-2185 Parameter IDMA Read, Short Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 tIRP Duration of Read Switching Characteristics: tIKHR IACK High after Start of Read1 tIKDH IAD15-0 Data Hold after End of Read2 tIKDD IAD15-0 Data Disabled after End of Read2 tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. Min Max Unit 0 15 15 0 10 0 15 ns ns ns ns ns ns ns IACK tIKR tIKHR IS tIRP IRD tIRDE IAD 15-0 PREVIOUS DATA tIKDH tIRDV tIKDD Figure 24. IDMA Read, Short Read Cycle REV. 0 -27- ADSP-2185 100-Lead TQFP Package Pinout 94 PF0 [MODE A] 93 PF1 [MODE B] 89 PF2 [MODE C] 100 A3/IAD2 99 A2/IAD1 96 PWDACK 98 A1/IAD0 91 PWD 95 BGH 80 GND 92 GND 90 VDD 77 D17 78 D18 79 D19 82 D21 83 D22 84 D23 85 FL2 88 PF3 81 D20 86 FL1 87 FL0 97 A0 76 D16 75 D15 74 D14 73 D13 72 D12 71 GND 70 D11 69 D10 68 D9 67 VDD 66 GND 65 D8 64 D7/IWR 63 D6/IRD 62 D5/IAL 61 D4/IS 60 GND 59 VDD 58 D3/IACK 57 D2/IAD15 56 D1/IAD14 55 D0/IAD13 54 BG 53 EBG 52 BR 51 EBR A4/IAD3 A5/IAD4 GND A6/IAD5 A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 A11/IAD10 1 2 3 4 5 6 7 8 9 PIN 1 IDENTIFIER A12/IAD11 10 A13/IAD12 11 GND 12 CLKIN 13 XTAL 14 VDD 15 CLKOUT 16 GND 17 VDD 18 WR 19 RD 20 BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 ADSP-2185 TOP VIEW (Not to Scale) RFS1 39 DR1 40 GND 41 SCLK1 42 ERESET 43 RESET 44 IRQL0+PF5 27 ECLK 47 ELOUT 48 IRQL1+PF6 29 IRQ2+PF7 30 DT0 31 TFS0 32 RFS0 33 DR0 34 SCLK0 35 IRQE+PF4 26 TFS1 38 EINT 50 EMS 45 GND 28 EE 46 ELIN 49 VDD 36 DT1 37 -28- REV. 0 ADSP-2185 The ADSP-2185 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. TQFP Pin Configurations TQFP Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name A4/IAD3 A5/IAD4 GND A6/IAD5 A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 A11/IAD10 A12/IAD11 A13/IAD12 GND CLKIN XTAL VDD CLKOUT GND VDD WR RD BMS DMS PMS IOMS CMS TQFP Number 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name IRQE + PF4 IRQL0 + PF5 GND IRQL1 + PF6 IRQ2 + PF7 DT0 TFS0 RFS0 DR0 SCLK0 VDD DT1 TFS1 RFS1 DR1 GND SCLK1 ERESET RESET EMS EE ECLK ELOUT ELIN EINT TQFP Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name EBR BR EBG BG D0/IAD13 D1/IAD14 D2/IAD15 D3/IACK VDD GND D4/IS D5/IAL D6/IRD D7/IWR D8 GND VDD D9 D10 D11 GND D12 D13 D14 D15 TQFP Number 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name D16 D17 D18 D19 GND D20 D21 D22 D23 FL2 FL1 FL0 PF3 PF2 [Mode C] VDD PWD GND PF1 [Mode B] PF0 [Mode A] BGH PWDACK A0 A1/IAD0 A2/IAD1 A3/IAD2 REV. 0 -29- ADSP-2185 ORDERING GUIDE Part Number ADSP-2185KST-115 ADSP-2185BST-115 ADSP-2185KST-133 ADSP-2185BST-133 Ambient Temperature Range 0C to +70C -40C to +85C 0C to +70C -40C to +85C Instruction Rate (MHz) 28.8 28.8 33.3 33.3 Package Description 100-Lead TQFP 100-Lead TQFP 100-Lead TQFP 100-Lead TQFP Package Option* ST-100 ST-100 ST-100 ST-100 *ST = Plastic Thin Quad Flatpack (TQFP). OUTLINE DIMENSIONS Dimensions shown in inches and millimeters. 100-Lead Metric Thin Plastic Quad Flatpack (TQFP) (ST-100) 0.640 (16.25) 0.630 (16.00) TYP SQ 0.620 (15.75) 0.555 (14.05) 0.551 (14.00) TYP SQ 0.547 (13.90) 0.476 (12.10) 0.474 (12.05) TYP SQ 0.472 (12.00) 100 1 76 75 0.063 (1.60) MAX 0.024 (0.75) 0.022 (0.60) TYP 0.020 (0.50) SEATING PLANE 12 TYP TOP VIEW (PINS DOWN) 0.004 (0.102) MAX LEAD COPLANARITY 0 - 10 25 6 4 26 51 50 0.007 (0.177) 0.005 (0.127) TYP 0.003 (0.077) 0.020 (0.50) BSC LEAD PITCH 0.010 (0.27) 0.009 (0.22) TYP 0.006 (0.17) LEAD WIDTH -30- REV. 0 -31- -32- C2993-10-3/97 PRINTED IN U.S.A. |
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